The invention relates to a data conversion system, and more particularly to a sigma-delta modulator, data conversion system and method with dynamic element matching logic.
Data conversion techniques have been in existence for many years, and their use has become widespread. Converters used, such as a digital-to-analog (D/A) converter or an analog-to-digital (A/D) converter, have found homes in applications such as communication systems, consumer and professional audio, and precision measurement devices.
Sigma-delta modulator (SDM), an A/D converter also known as an oversampling A/D converters characterized by high dynamic range and high resolution, has been successfully applied in communication and other signal processing areas. One-bit sigma-delta modulators have been popular in the past for their inherent linearity. However, to fulfill the demand for higher resolution and wider bandwidth without increasing the oversampling ratio, it is necessary to utilize multi-bit sigma-delta modulators which also reduce quantization noise power. Nevertheless, the major drawback of the multi-bit sigma-delta modulators is non-linearity stemming from the mismatching between the D/A elements in the feedback multi-bit D/A converter of the SDMs. FIG. 1a shows a conventional N-bit sigma-delta modulator 10 wherein N is an integer greater than 2. The N-bit sigma-delta modulator 10 comprises a summing junction 12, a loop filter 14, a N-bit quantizer 16 and a N-bit D/A converter 18. The summing junction 12 receives an analog input signal Vin and subtracts an analog feedback signal VFB from the N-bit D/A converter 18. The loop filter 14 coupled to the summing junction 12, receiving the output of the summing junction 12, includes cascaded analog integrator stages and generates a filtered analog output to the N-bit quantizer 16. The N-bit quantizer 16 then quantizes the analog output of the loop filter 14 and generates a digital code, also fed back to the N-bit D/A converter 18. The N-bit D/A converter 18, having a plurality of D/A elements, converters the digital code to the analog feedback signal VFB to the summing junction 12. The mismatching between the D/A elements in the N-bit D/A converter 18, such as capacitors, resistors, current sources and the like, due to manufacturing variations, imperfections in materials used, changes in temperature, humidity, degradation and so on, causes non-linearity in the feedback path, which manifests itself as distortion and noise at output.
One approach addressing the non-linearity problem of the multi-bit D/A converter is dynamic element matching (DEM). FIG. 1b shows a conventional N-bit sigma-delta modulator 20 utilizing the DEM technique. FIG. 1b is similar to FIG. 1a except for the dynamic element matching logic 22 coupled between the N-bit quantizer 16 and N-bit D/A converter 18. The dynamic element matching logic 22 randomly selects the D/A elements in the N-bit D/A converter 18 to distribute the non-linear error across the spectrum. Moreover, a particular DEM technique is data weighted average (DWA). FIG. 2 illustrates the principle of the DWA technique which can be employed in the dynamic element matching logic 22 of FIG. 1b with a 3-bit D/A converter having 8 D/A elements, wherein the y-axis denotes the input digital code at every time slot and the grey blocks in x-axis and the numerals therein denote corresponding selected elements and selected order. The DWA logic regularly selects the D/A elements one by one at a predetermined turn according to the input digital code. For example, when the input digital code is 5 at t1, the DWA logic selects D/A elements, C1 to C5 in turn, and at the next time slot, t2, with input digital code, 2, the DWA logic selects D/A elements, C6, proceeding to the previous last selected element, C5, and then C7. The selection of D/A elements proceeds in the direction of the arrow. The DWA technique averages the participation of each D/A element, thus shifting DAC (D/A converter) mismatch error to a higher frequency band and providing easy implementation and first order noise shaping.
However, since the DWA logic is dependent upon the amplitude of the input digital code, in-band tones occur when the input amplitude is small, reducing both the SNDR (signal-to-noise plus distortion ratio) and SFDR (spur free dynamic range) significantly. FIG. 3a and FIG. 3b show the output frequency spectrum of a third order sigma-delta modulator having the 3-bit DAC in FIG. 1 and utilizing conventional DWA technique with the input signals of −2 dB and −45 dB respectively. By comparing FIG. 3b to FIG. 3a, it can be observed that in-band tones occur in FIG. 3b, due to the sigma-delta modulator generating periodic feedback signal with small input signal amplitude, whereas the mismatch errors between D/A elements become periodic, causing in-band aliasing tones. Thus, it is desirable to have a DWA logic, eliminating the in-band tones caused when the input signal amplitude is small.